module data_mem (
  input clk,
  input rst,
  input mem_write,
  input [31:0] addr,
  input [31:0] write_data,
  output[31:0] read_data
);
  reg[31:0] DM[0:255];
  integer i;
  always @(posedge clk, posedge rst) begin
      if(mem_write) begin
        DM[addr[9:2]] <= write_data;
      end
      if(rst) begin
        for(i=0; i<255; i++)
          DM[i] <= 0;
      end
  end

  assign read_data = DM[addr[9:2]];

endmodule